1. Field of the Invention
The present invention relates to an electronic circuit including a bus and more particularly, to a method and system for establishing synchronization of data transfer between buses having different operating frequencies.
2. Description of the Related Art
In general, an information processor such as a personal computer or workstation has a hierarchical bus structure such that different buses have different data transmission rates and operating frequencies. For example, a host bus connected to a CPU, cache memory or main memory has the highest data transmission rate. The system bus having the second highest data transmission rate is connected to an I/O interface such as a CRT display interface or a hard disk interface.
The higher the operating frequency of a bus is, the more the bus is influenced by an electrical load such as wiring capacitance or parasitic capacitance, which disadvantageously leads to the fact that the amount of electronic equipment to be connected to the bus must be limited and also the bus manufacturing cost is increased. When the bus employs a hierarchical structure, the cost of the associated information processor can be reduced. However, realization of the above hierarchical structure requires a technique that enables transfer of bus signals including control and data signals between buses having different operating frequencies. To this end, for the purpose of normally transmitting the bus signals to the other bus in data transfer between synchronous buses, timing conversion is carried out therebetween so that a time in which data can be made electrically valid, i.e., a setup time, is satisfied on the respective buses. Such operation is referred to as "bus synchronization".
In general, further, the timing of sampling a bus signal is different between buses having different operating frequencies, and therefore bus synchronization causes an additional waiting time. The waiting time, which is known as "synchronization overhead", increases the time necessary for transmission of signals between the buses, which results in reduction in data transmission performance between the buses. For this reason, reduction of the synchronization overhead is demanded in the bus synchronization.
FIG. 2 is a block diagram of an example of an information processor based on a prior art bus synchronizing system, which includes a host bus 100 operated in synchronism with a clock CLK1 having an operating frequency f1 and a system bus 200 operated in synchronism with a clock CLK2 having an operating frequency f2.
In the drawing, the clock CLK1, which is issued from an oscillator (OSC) 80, is divided by a frequency divider 50 having a frequency division ratio N (natural number) to generate the clock CLK2. The operating frequency f1 of the clock CLK1 and the operating frequency f2 of the clock CLK2 have a relationship of f2=f1/N.
A CPU 10 is connected to the host bus 100 and an I/O interface 20 is connected to the system bus 200 so that signal transmission between the CPU 10 and the I/O interface 20 is carried out through a bus synchronizing circuit 60 which in turn is operated by the clock CLK1.
An example of the prior art bus synchronizing system will be explained in connection with FIG. 3. In this case, the frequency division ratio N is set at 4. When it is desired to transfer data from the host bus 100 to the system bus 200, timing conversion is carried out to prevent unstable data transfer, which is called "synchronization". The I/O interface 20 receives a system bus signal 201 in synchronism with a rising edge of the clock CLK2. For normal data transmission, only passage of at least a setup time tsu1 after a change in the system bus signal allows the I/O interface 20 to take in the system bus signal 201.
An explanation is offered next regarding how to shift the phase of the clock CLK2 in order to remove the synchronization overhead. When a host bus signal 101 output from the CPU 10 becomes valid at the time T501, the bus synchronizing circuit 60 asserts a phase shift request signal 602 associated with the clock CLK2 (that is, puts the phase shift request signal 602 in its active level H). At the time T502 of the first rising edge of the clock CLK1 after the above assertion, the bus synchronizing circuit 60 outputs the system bus signal 201. In this case, the circuit delay causes the system bus signal 201 to change at the time T503 corresponding to a time tdly1 after the time T502. Further, the frequency divider 50 phase-shifts the clock CLK2 from the time T502 to shift the clock CLK2 from its L level to H level at the time T504 after a predetermined time tsft1. The predetermined time tsft1 may be a natural number multiple of the period of the clock CLK1.
When the clock CLK2 shifts from its L level to H level at the time T504, the setup time tsu1 from the time T503 is satisfied, so that the I/O interface 20 can normally sample the system bus signal 201.
An explanation will then be made regarding a case where such a phase shift as mentioned above is not carried out. When such phase shift of the clock CLK2 as mentioned above is not effected, the bus synchronizing circuit 60 waits for the first rising edge time point T506 of the clock CLK2 after the time point T502, outputs the system bus signal 201, and then the I/O interface 20 samples the system bus signal 201 at the time T507. A time duration between the time T502 and T506 is a waiting time given for the synchronization, i.e., synchronization overhead.
In this way, there is known a bus synchronizing system that the time T504 at which the clock CLK2 rises is always given after the predetermined time tsft1, regardless of the phase state at the time of starting the bus synchronization, whereby the necessary setup time tsu1 is satisfied and the synchronization overhead is reduced. Electronic circuits for realizing such a synchronizing system includes a chip set 82350DT (a trademark, manufactured by Intel Corporation, U.S.A.) for performing host bus/EISA bus conversion. For details of the chip set, refer to a data book (82350DT EISA CHIP SET, Order Number: 290377-003) issued from Intel Corporation, U.S.A.
In the aforementioned prior art bus synchronizing system, since the clock CLK1 of the frequency f1 is frequency-divided to generate the clock CLK2 of the frequency f2, the frequency f2 of the clock CLK2 is lower than the frequency f1. For this reason, when it is desired to transmit a signal from the bus having the low operating frequency f2 to the bus having the high operating frequency f1, the phase shift of the clock CLK1 also affects the clock CLK2. Therefore, it is impossible to perform such phase shifting operation as mentioned above over the clock CLK1 and thus it is impossible to shorten the synchronization overhead.
Further, the phase shift is always carried out over the clock CLK2, so that, regardless of the fact that the setup time is sufficiently satisfied until the next rising edge, that is, the phase shift becomes unnecessary depending on a phase relationship between the clocks CLK1 and CLK2, the phase shift is carried out and the corresponding synchronization overhead is generated.
Furthermore, since a relationship of f2=f1/N (N: natural number) is satisfied between the frequency f1 of the clock CLK1 and the frequency f2 of the clock CLK2, combinations of these frequencies f1 and f2 are limited.